Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell
نویسندگان
چکیده
A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by combination of transmission gate (TG), pass transistor logic (PTL), float techniques. Using the proposed cell, 4:2 compressor implemented its performance investigated under diverse circumstances voltage, temperature, driving. The process corners are evaluated through process-voltage-temperature (PVT) variations Monte Carlo method (MCM), respectively. accuracy reliability confirmed carefully. Utilising FA compressor, an efficient 8-bit subtractor for bioimage processing, in particular difference detection images. mechanism to improve digital signal processors (DSPs) addition subtraction two images their difference. quality resulted image confirms efficiency circuits method. high makes them promising candidate next generation integrated (ICs) applicable medical processing.
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ژورنال
عنوان ژورنال: IET circuits, devices & systems
سال: 2022
ISSN: ['1751-858X', '1751-8598']
DOI: https://doi.org/10.1049/cds2.12117